(a) Field of the Invention
The present invention relates to an anti-reflection structure for a conductive layer in a semiconductor device and, more particularly, to an anti-reflection structure suited for forming a conductive layer pattern having an accurate width in a semiconductor device.
(b) Description of the Related Art
With the development of higher integration of semiconductor devices, for example in a MOSFET device, it has become more and more important to form an interconnect pattern having an accurate width, regardless of the situation wherein the line width and the line pitch have become smaller and smaller.
In a MOSFET device, the gate electrodes are generally configured using a photolithographic and etching technique wherein a mask pattern is accurately transferred onto a conductive layer by using an exposure light. In order to prevent the transfer error during the photolithographic step using the exposure light, an anti-reflection layer is generally formed on the conductive layer to be patterned.
Example of using the anti-reflection layer will be described with reference to the process for patterning gate electrodes in DRAM memory cells.
FIG. 1 shows a sectional view of a DRAM memory cell. The memory cell generally designated by numeral 10 includes a silicon substrate 12, an isolation film 14 formed thereon for isolation of device areas, a MOSFET 16 formed in each device area, and a capacitor 18 overlying the MOSFET 16. The MOSFET 16 includes a gate electrode 24 including a gate electrode layer 20, and a silicon nitride layer 22 formed thereon. A side wall structure 26 is formed on both the sides of the gate electrode 24.
A contact plug 28 is disposed in contact with a diffused region (not shown) formed in the surface region of the silicon substrate 12. The gate electrode layer 20 is connected to a word line (not shown). The silicon nitride layer 22 acts as an etch stopper during the etching step for forming a through-hole receiving therein the contact plug 28. The gate electrode 24 is also disposed on the isolation region 14 for convenience of the fabrication process.
The capacitor 18 overlies the MOSFET 16 with an intervention of an interlayer dielectric film 30. The capacitor 18 includes a capacitor contact 32 penetrating the interlayer dielectric film 30 to be in contact with the contact plug 28, a bottom electrode 34 in contact with the capacitor contact 32, and a top electrode 38 opposing the bottom electrode 34 with an intervention of a capacitor insulator film 36.
FIGS. 2A to 2F show consecutive steps for fabrication of the DRAM memory cell 10 of FIG. 1. As shown in FIG. 2A, an element isolation film 14 is formed on a silicon substrate 12 for isolation of device areas, followed by consecutively forming thereon a gate electrode layer 20, a first silicon nitride layer 22, an anti-reflection layer 40 including a lower silicon oxide nitride film 40a and an upper silicon oxide film 40b, and a photoresist film 42.
Subsequently, a gate mask pattern is transferred onto the photoresist film 42, followed by patterning thereof to form an etching mask 44, as shown in FIG. 2B. By using the etching mask 44, as shown in FIG. 2C, the silicon oxide film 40b, the silicon oxide nitride film 40a, silicon nitride layer 22 and the gate electrode layer 20 are selectively etched for patterning, thereby forming a gate electrode structure 46.
A second nitride film is then formed on the entire surface including the gate electrode structure 46, followed by selective etching of the second nitride film to form side walls 26 on the gate electrode structure 46, and etching of the silicon nitride layer 40b and the silicon oxide nitride film 40a to remove the same from the gate electrode structure 46, as shown in FIG. 2D. Thereafter, an interlayer dielectric film 48 made of silicon oxide is deposited and subjected to CMP thereof to obtain a smoothed top surface.
Then, the interlayer dielectric film 48 is selectively etched using a self-alignment contact etching technique having a high selective ratio between the first silicon nitride layer 22 and the interlayer dielectric film 48, whereby through-holes 49 are formed in the interlayer dielectric film 48, as shown in FIG. 2E, to expose the surface regions of the silicon substrate. In the self-alignment contact etching step, the first silicon nitride layer 22 acts an etch stop layer.
Then, a conductive layer is deposited on the entire surface to fill the through-holes 49 and etched-back to obtain contact plugs 28 as shown in FIG. 2F.
Subsequently, as shown in FIG. 1, an interlayer dielectric film 30 is deposited, followed by a known process for forming the capacitor contact 32 and the capacitor 18.
In the above conventional anti-reflection structure, the anti-reflection layer 40 including the silicon oxide nitride film 40a and the silicon nitride layer 40b is formed on the gate electrode layer 20 with an intervention of the silicon nitride layer 22, as detailed in FIG. 3A. As an alternative structure, the anti-reflection layer 40 may be formed between the gate electrode layer 20 and the silicon nitride layer 22, such as shown in FIG. 3B.
In the conventional anti-reflection structure as described above as well as the alternative structure, the thickness of the anti-reflection layer 40 is determined based on several factors including the materials for the gate electrode layer 20, the thickness of the silicon nitride layer 22, and the types and materials for the photoresist film. Thus, it is difficult to determine the optimum value for the thickness for the anti-reflection layer, whereby the conventional anti-reflection layer cannot demonstrate a sufficient function during the exposure.
In other words, there is a problem in the conventional technique in that an inaccurate pattern is transferred onto the photoresist film due to the adverse effects of the reflected light generated during the exposure of the photoresist film. The inaccurate pattern involves irregularity of the gate width in the DRAM memory cells and of the line width in general semiconductor devices.
More specifically, in the anti-reflection structure of FIG. 3A, assuming that the design thickness of the silicon nitride layer 22 is 2000 angstroms, for example, the silicon oxide nitride film 40b should have a thickness of 500 angstroms in order to obtain a minimum variation for the gate width.
In this case, i.e., wherein the silicon oxide nitride film 40b has a thickness of 500 angstroms, the variation of the gate width may be suppressed to within 8 nm if the silicon nitride layer 22 has an exact thickness of 2000 angstroms. However, if the silicon nitride layer 22 has an actual thickness of 1800 or 2200 angstroms, the gate width variation amounts up to 40 nm. A typical case for this example is shown in FIG. 4A, wherein the top surface of the gate electrode layer 20 has an irregularity to cause a depression on the silicon oxide film 40b acting as the underlying layer for the photoresist film 44. This in turn causes an irregularity of the pattern width of the photoresist film 44, wherein the pattern width increases at the depression and decreases at the elevation of the underlying layer.
In the anti-reflection structure of FIG. 3B, assuming similarly that the design thickness of the silicon nitride layer 22 is 2000 angstroms, the silicon oxide nitride film 40b should have a thickness of 500 angstroms in order to obtain a minimum variation for the gate width.
In this case, i.e., wherein the silicon oxide nitride film 40b has a thickness of 500 angstroms, the variation of the gate width may be suppressed to within 8 nm if the silicon nitride film layer 22 has an exact thickness of 2000 angstroms. However, if the silicon nitride layer 22 has an actual thickness of 1800 or 2200 angstroms, the gate width variation amounts up to 50 nm or 54 nm. A typical case for this example is shown in FIG. 4B, wherein the top surface of the gate electrode layer 20 has an irregularity to cause a depression on the silicon nitride layer 22 acting as the underlying layer for the photoresist film 44. This in turn causes the irregularity of the pattern width of the photoresist film 44, wherein the pattern width increases at the depression and decreases at the elevation of the underlying layer.
In the above example, the problem in the anti-reflection structure is described with reference to patterning of a two-layer structure including a gate electrode layer and a silicon nitride layer in a MOSFET device. However, the problem in the anti-reflection structure is common to patterning of any layered structure in semiconductor devices so long as the layered structure includes a conductive layer and an insulator layer.
It is an object of the present invention to provide an anti-reflection structure for a conductive layer in a semiconductor device, which is capable of suppressing variation of the line width caused by exposure light.
It is another object of the present invention to provide a method for forming an anti-reflection structure in a semiconductor device.
The present invention provides a semiconductor device including a substrate, a conductive layer overlying the substrate, a first anti-reflection layer, a first insulator layer and a second anti-reflection layer consecutively formed on the conductive layer, the conductive layer, first anti-reflection layer, the first insulator layer and the second anti-reflection layer are patterned to have a common pattern.
The present invention also provides a method including the steps of forming a conductive layer overlying a substrate, consecutively forming a first anti-reflection layer, a first insulator layer and a second anti-reflection layer on the conductive layer, forming a mask pattern on the second anti-reflection layer by using a photolithographic technique, and patterning the second anti-reflection layer, the first insulator layer, the first anti-reflection layer and the conductive layer by using the mask pattern.
In accordance with the present invention, each of the first and second anti-reflection layers sandwiching the first insulator layer cancels the reflected light reflected from the other of the first and second anti-reflection layer even in the case of a larger variation for the thickness of the first insulator, layer.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.